In recent years, stacked cascode amplifiers, which use a plurality of transistors arranged as a stack (stacked transistors) in an amplification stage of the amplifiers, have become predominant in radio frequency (RF) applications where high power, high voltage outputs are desired. Due to the higher number of transistors in the stack, voltage handling performance of the amplifier is increased, thereby allowing the high power, high voltage outputs. Stacked or cascoded amplifiers are also common in low noise amplifiers where the benefits to gain an isolation as well as linearity are realized in addition to voltage handling. Since the stacked transistors comprise individual low voltage transistors which can tolerate a voltage substantially lower than the output voltage of the amplifier, it is important to bias the low voltage transistors of the stack so to maintain operation within their tolerable voltage range. Such voltage compliance of the low voltage transistors of the stack must be maintained whether the amplifier operates in an active mode transmitting a signal, or in a standby mode not transmitting a signal. In addition, as performance characteristics of such amplifiers may be based on the biasing voltages to the transistors of the stack, it is important to quickly stabilize such biasing voltages so to reduce a transition phase between different operating modes of the amplifiers. This in turn can allow reduction in settling times of the amplifier when switching, for example, between activated and deactivated states of the amplifier, bands of operation, and/or gain settings of the amplifier, and therefore allow for quicker connections and reduced data loss due to longer settling times of the amplifier.
FIG. 1 shows a simplified schematic of a prior art stacked cascode (RF) amplifier (100). As shown in FIG. 1, the stacked cascode amplifier (100) can comprise a stack of n FET transistors (M1, M2, . . . , Mn) that include an input transistor M1, and cascode transistors (M2, . . . , Mn), including an output transistor Mn. An input RF signal, RFin, provided at an input terminal of the amplifier (100) is routed to a gate of the input transistor, M1, and is amplified by the amplifier (100). A corresponding amplified output RF signal, RFout, is provided at a drain of the output transistor, Mn, and routed to an output terminal of the amplifier. Decoupling capacitors (Cin, Cout) can be used to decouple low frequency (e.g., DC) biasing voltages provided to the stack of transistors (transistor stack) from the RFin and RFout signals. A supply voltage, VDD, is provided to the drain of the output transistor, Mn, through an inductor, L, and a reference potential (e.g., GND), representing for example an AC ground, is connected to a source of the input transistor M1. In some implementations, as for example described in the above referenced U.S. Patent Publication No. 2018/0083578, the disclosure of which is incorporated herein by reference in its entirety, the source of the input transistor may be optionally connected to the AC ground via degeneration elements, such as, for example, the degeneration inductor Ldeg shown in FIG. 1. A person skilled in the art is well aware of such implementations, as used, for example, in design of low noise amplifiers (LNA's) of a receive path of an RF front end system.
With continued reference to FIG. 1, biasing voltages (Vg2, . . . , Vgn) are provided to gates of the cascode transistors (M2, . . . , Mn) through resistors (R2, . . . , Rn) connected to the gates of the cascode transistors, and a bias voltage Vg1 is provided to the gate of the input transistor M1. Although not shown in FIG. 1, biasing voltage Vg1 may also be provided to the gate of the input transistor via a resistor, as shown, for example, in FIG. 2. Such resistors may be used, in combination with the gate capacitors (Gg2, . . . , Cgn), to decouple any noise from a biasing circuit that generates the biasing voltages into the stacked cascode amplifier and/or decouple any residual RF signal at gates of the cascode transistors (M2, . . . , Mn) from the biasing circuit. Gate capacitors (Cg2, . . . , Ggn) are coupled between gates of the cascode transistors (M2, . . . , Mn) and the reference potential, GND. It should be noted that n is an integer number that can be of any value equal to, or greater than, two. A value of n may be based on a voltage withstand capability of the transistors (M1, M2, . . . , Mn) and a high value of an RF voltage at the drain of the output transistor Mn. More description of such prior art stacked cascode amplifier (100) can be found, for example, in the above referenced U.S. Pat. No. 7,248,120, the disclosure of which is incorporated herein by reference in its entirety.
Biasing voltages to the stacked cascode amplifier (100) of FIG. 1 may be provided by biasing circuits according to various implementations known in the art. Some such biasing circuits are described, for example, in the above referenced U.S. Pat. Nos. 9,843,293, 7,248,120, 9,716,477, and U.S. Patent Publication No. 2018/0083578, the disclosures of which are incorporated herein by reference in their entirety. Also, as described, for example, in the above referenced U.S. Pat. No. 9,716,477, the supply voltage VDD, may be a fixed voltage or a variable voltage. The variable voltage may be provided, for example, via a DC-DC converter or a voltage regulator. In some exemplary configurations, the supply voltage can vary under control of an external control signal. In some configurations, the control signal can be a function of an envelope signal of the input RF signal, RFin, or the output RF signal, RFout. Detailed description of biasing methods and apparatus for stacked transistor amplifiers operating from a variable supply voltage can be found, for example, in the above referenced U.S. Pat. Nos. 9,219,445, and 9,413,298, the disclosures of which are incorporated herein by reference in their entirety.
FIG. 2 shows an exemplary prior art biasing circuit (210) that provides a biasing voltage, Vg2, to the gate of the cascode transistor M2 for an exemplary case of a stacked cascode amplifier (M1, M2) with a non-limiting height of n=2. It should be noted that as discussed above in relation to the stacked cascode amplifier (100) of FIG. 1, such height can be represented by any number n that is equal to, or greater than, two. Accordingly, each of the gate voltages to the cascode transistors (M2, . . . , Mn) may be provided via a biasing circuit that is similar to one depicted in FIG. 2 (e.g., FIG. 5A later described). Also, not shown in FIG. 2, is biasing of the gate of the input transistor, M1, which is beyond the scope of the present disclosure, and which may be provided independently from the biasing voltage Vg2. Some exemplary biasing circuits for biasing the gate of the input transistor, M1, can be found, for example, in the above referenced U.S. Pat. No. 9,716,477 and U.S. Patent Publication No. 2018/0083578, the disclosures of which are incorporated herein by reference in their entirety.
As can be seen in FIG. 2, the biasing circuit (210) comprises a current mirror branch formed by a reference cascode circuit (M′1, M′2) that is a scaled down (e.g., 1/20th or less, such as, for example, 1/30th, 1/40th, . . . , 1/Nth with N≥20) replica version of the cascode amplifier circuit (M1, M2), so that a current (Icore) flowing through the transistors (M′1, M′2) is mirrored to provided a current (Icore*N) flowing thorough the transistors (M1, M2). The transistors M′1 and M′2 are smaller size versions of the transistors M1 and M2 respectively, so that for same biasing voltages applied to the amplifier circuit (M1, M2) and the reference circuit (M′1, M′2), a ratio of the biasing currents through the reference circuit (M′1, M′2) and the amplifier circuit (M1, M2) is substantially equal to a ratio of the sizes of the transistors of the two circuits. Accordingly, if a current Icore flows through the reference circuit (M′1, M′2), then a current Icore*N flows through the amplifier circuit (M1, M2), where N is a ratio of the size of the amplifier circuit to the size of the reference circuit, or in other words, N is a scaling factor between the two circuits. For example, if the transistors M′1, M′2 of the cascode reference circuit (M′1, M′2) are 1/100 of the size of the transistors M1, M2 of the cascode amplifier (M1, M2) respectively, the scaling factor N would be 100. It should be noted that the size of such transistors may be defined in terms of different aspects of the transistors, such as, for example, transistor area, gate length, gate width, etc., so long as a same aspect of the transistors is compared.
With further reference to FIG. 2, gate voltage Vg2 for biasing of the cascode transistor M2 is provided via a combination of a resistive voltage divider (Rtop, Rbot), a diode-connected transistor, M_Diode, and current sources IcasP and IcasN. The current source IcasP is coupled to a common gate-drain node of the diode-connected transistor, M_diode, and the current source IcasN is coupled to a source node of the diode-connected transistor, M_diode. The resistive voltage divider (Rtop, Rbot) generates a reference voltage, Vref2, at the source node of the diode-connected transistor, M_diode, based on a supply voltage VDD. In turn, the diode-connected transistor, M_diode, generates the gate voltage, Vg2, that is one diode drop above the reference voltage, Vref2. Finally, current from IcasP or IcasN serve to provide a current for the diode connected transistor M_diode and also charge or discharge the Vg2 node such that Vg2 is equal to Vref2+Vdiode, where Vdiode is the voltage across the diode-connected transistor M_diode.
With continued reference to FIG. 2, by selecting the diode-connected transistor, M_diode, to have a same current density as the cascode transistors M′2 and M2, a person skilled in the art would understand that in a steady-state condition of the circuit shown in FIG. 2, where the reference voltage, Vref2, provided by the resistive voltage divider (Rtop, Rbot) and the gate voltage Vg2 are steady, a gate-to-source voltage, Vgs, of the diode-connected transistor, M_diode, is equal to a gate-to-source voltage, Vgs, of the cascode transistors M′2 and M2. In turn, this allows to precisely set, for example, a drain voltage of the input transistor M1 to be equal to the reference voltage, Vref2. As used herein, and as it is well known to a person skilled in the art, the expression “current density” refers to a ratio of a current through a transistor (e.g., drain current) to a size of the transistor, where the size can be any of a transistor area, a gate length, a gate width, etc.
During the steady-state condition of the circuit shown in FIG. 2, the voltage Vref2 and the voltage Vg2 are substantially fixed, and therefore no current flows into the gate capacitor Cg2 and no current flows from the source of the diode-connected transistor M_diode into the resistive voltage divider (Rtop, Rbot). Accordingly, the currents IcasP and IcanN are equal.
Considering a transition phase of the circuit shown in FIG. 2, defined by a change of the biasing voltage Vg2 corresponding to a desired operation of the cascode amplifier (M1, M2). Such transition phase may correspond to, for example, an activation state of the amplifier after a deactivation state of the amplifier, or a change in a frequency band (and therefore operating frequency) of the amplifier, or a change in a gain of the amplifier. As the reference voltage, Vref2, sets the biasing voltage, Vg2, such transition phase may include changing values of the resistors Rtop and/or Rbot so to change the reference voltage, Vref2. As can be seen in FIG. 2, such resistors may be programmable/settable resistors, either according to discrete values or continuous values. It should be noted that although in the exemplary case of the prior art configuration of FIG. 2, a resistive voltage divider is used to generate the reference voltage, Vref2, a person skilled in the art would know that other circuit implementations may also be used, such as, for example, circuits using an operational amplifier and/or digital-to-analog devices. Furthermore, in a case where the transition phase corresponds to activation of the amplifier after a deactivation, or vice versa, the transition phase may also include activation/deactivation of the current sources (e.g., Icore, IcasP, IcasN) which may have been turned off during the deactivated states of the cascode amplifier (M1, M2) for power conservation purposes.
During the transition phase of the circuit shown in FIG. 2, current from IcasP may flow into the gate capacitor, Cg2, to charge up the capacitor to a new (higher) voltage value of Vg2. Alternatively, a current may flow from the capacitor Cg2 into the diode-connected transistor to discharge the capacitor for a new (lower) voltage value of Vg2. For this, a maximum current available for the charging or discharging of the capacitor Cg2 is provided by the maximum current of the current source IcasP and the maximum current of the current source IcasN respectively. As such maximum currents are set to be sufficiently low so as to not drain substantial power from the supply VDD (and therefore from a battery generating VDD), charging and discharging speed of the capacitor Cg2, and therefore settling time of the amplifier's biasing conditions, may be compromised in favor of lesser power consumption of the circuit. A motivation for the teachings according to the present disclosure is to remove a need for such compromise, and therefore reduce the settling times while maintaining a low power consumption of the circuit.